Method and apparatus for testing integrated circuits

ABSTRACT

There is an IC (integrated circuit) testing device  11  that receives singulated ICs from a singulation station&#39;s bottom table  44 , where an IC  15  has slid down onto loading ramp or track  16 . The IC will slide into test station  18 , where stop pin  22  has been inserted to stop the IC in DUT (device under test) station  20 . In the DUT station, the IC is securely held in position by an extractor bar  26 , insertion bar  28 , and a part guide  24 . Thereby, test cite station  18  will move downward and insert IC  15  into testing socket  30 . After testing the IC, testing station  18  returns upward with IC in the same secured position. Pin  22  will be removed to allow the IC to slide into part holding station  31 . If the IC was not defective, pin  32  will be removed to allow the IC to slide onto track  36  of the IC separator station  34 . While the test cite station  18  is in the up position a second IC is slid along track  16  and loaded into DUT cite  20  being readied for the next test cycle. However, if the first IC was found to be defective, pin  32  will be positioned so as to stop the IC from sliding onto track  36 . Thereby, the test cite  18  will proceed to the down position to test the second IC, and simultaneously pin  32  will be removed to now allow the defective IC to slide onto track  38 . The second IC has now completed its testing and is ready to proceed to the remainder of the cycle.

FIELD OF THE INVENTION

The present invention relates to integrated circuits ICs). Particularly,this invention relates to IC quality testing equipment. Uniquely, thereis a method and device that can detect defective ICs that are coming offof an IC singulation station or work process.

BACKGROUND OF THE INVENTION

FIG. 1 illustrates a representative portion of a semiconductor chip trimand pin forming machine. One can purchase such a machine from ASM AsiaInc., 4302 E. Broadway Rd., Phoenix, Ariz., model AP50, or fromPrecision Technologies Inc. 1725 De La Cruz Blvd. #4, Santa Clara,Calif. 95050, models Matrix SS, FS, or FM. FIG. 1 identifies thefollowing elements: Platen 40 is the portion of the press-type machineto move up and down to stamp in the desired forming and trimmingoperations. Vertical action rod 42 is attached to a means for movingplaten 40 into contact with the non movable table 44. IC forming andcutting die 44 45are mounted to both the platen 40 and table 44. ICloading station 50 receives a set of ICs usually from the plasticencapsulation station and they are attached on a typical singleleadframe. Trim stations 60 will trim off the excess encapsulationmaterial and metal leadframe portions. Forming stations 70 will bend theleads of the ICs into various configurations like “SOJ” or DIP.Singulation station 80 will completely separate the ICs from theleadframe to become single packages or devices 10.

One skilled in the art will be familiar with the operation of themachine and its variations. Specifically, all processes or work stationactivities take place on a paced operation which is timed to theplaten's 40 up and down cycles. When plate 40 is up, the conveyor systemwill move the leadframe/s forward, readying the ICs for their next stepof operation or simply loading new leadframes in preparation for theassembly process. When the platen 40 is “punched down”, the various workstations perform their various designed operations, cutting, shaping,cleaning, separating etc.

After the ICs have been separated, they are collected and forwarded tosubsequent work stations. Such as lead finishing or solder coating,primary testing involving a large amount of tests and expensive slowequipment, and acceptable quality level tests examining for physicaldefects in the packages/ICs. Thereafter, the ICs are tested to determinewhich ones are defective.

PROBLEM

After an IC has been singulated or separated from the other ICs, thereis still remaining a lot of work or investment that need to be put intoeach IC before they are completely done. However, there are many defectsthat could have already occurred up to the point of singulating the ICs.Typically, the ICs are tested for defects after completing the fullproduction process occurring well after the singulation stage. A few ofthe main reasons for testing so late in the production cycle is that thetypical tests performed are costly and time consuming. There has notbeen any known method of or device for testing the ICs immediately aftersingulation of the ICs. Such a testing system would undoubtedly save agreat deal of time and money by not working on identified defective ICs.

It is noted that the above described problems, as well as otherproblems, are solved through the subject invention and will become moreapparent, to one skilled in the art, from the detailed description ofthe subject invention.

SUMMARY OF THE INVENTION

The invention is a method and an apparatus for controlling positioningof circuit before, during and after a circuit.

One skilled in the art will appreciate the advantage of the method ofand device for testing the ICs immediately after singulation of the ICs.Specifically, there is a method of and device for receiving thesingulated ICs and performing tests to separate defective ICs from therest of the ICs.

Other features and advantages of the present invention may become moreclear from the following detailed description of the invention, taken inconjunction with the accompanying drawings and claims, or may be learnedby the practice of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a related art illustration.

FIG. 2 is a general overall view of the invention.

FIG. 3 is a detailed illustration of the invention.

FIG. 4 is another detailed illustration of the invention.

It is noted that the drawings of the invention are not to scale. Thedrawings are merely schematic representations, not intended to portrayspecific parameters of the invention. The drawings are intended todepict only typical embodiments of the invention, and are therefore notrobe considered limiting of its scope. The invention will be describedwith additional specificity and detail through the use of theaccompanying drawings. Additionally, like numbering in the drawingsrepresent like elements within and between drawings.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws “to promote the progressof science and useful arts” (Article 1, Section 8 of the U.S.Constitution).

GENERAL EMBODIMENT

Referring to FIG. 2, there is a sectional side view of the IC testingdevice 11 comprising the following elements: There is a portion of asingulation station's bottom table 44, where an IC 15 has slid down ontoloading ramp or track 16. The IC will slide into testing station 18,where stop pin 22 has been inserted to stop the IC in DUT (device undertest) station 20. In the DUT station, the IC is securely held inposition by an extractor bar 2, insertion bar 28, and a part guide 24.Thereby, test cite station 18 will move downward and insert IC 15 intotesting socket 30. Typical testing sockets can be purchased from WellsElectronics, Inc. 1701 S. Main St., South Bend, IN 46613. After testingthe IC, testing station 18 returns upward with the IC in the samesecured position. Pin 22 will be removed to allow the IC to slide intopart holding station 31. If the IC was not defective, pin 32 will beremoved to allow the IC to slide onto track 36 of the IC separatorstation 34. While the test cite station 18 is in the up position asecond IC is slid along track 16 and loaded into DUT cite 20 beingreadied for the next test cycle. However, if the first IC was found tobe defective, pin 32 will be positioned so as to stop the IC fromsliding onto track 36. Thereby, the test cite 18 will proceed to thedown position to test the second IC, and simultaneously pin 32 will beremoved to now allow the defective IC to slide onto track 38. The secondIC has now completed its testing and is ready to proceed to theremainder of the cycle.

Referring to FIGS. 3 and 4, there are sectional views of the DUT stationin an upper and lower position. Further illustrated are the IC J shapedleads 42, and the insertion of the leads into the test sockets 30 andcontacting the test contacts 40.

It is noted that the testing device 11 can test a whole series of ICs ina parallel process, using side by side testing device stations.

It is further noted that there are only certain test that can beperformed in a typically short period of time. With the short cycle ofthe testing, the testing may keep pace with the ICs that are beingsingulated at a similarly fast rate.

In particular, there are several typical testing procedures that willidentify gross IC errors. For example, open and shorts are easily testedfor by loading data onto a diagonal in the memory array or performingother parametric testing. This will test for the proper function of eachcolumn and row of the device (IC). Other test check for proper currentat both lower and higher levels.

As a result, there are many defects that can be identified in a veryshort test cycle. Specifically, electro static discharge damage, massivearray failures, full row/-column failures, physically scratched die,blanks (where there is no die in the encapsulated IC), improper wirebonding to the die, and IC lead/pin failures, to name a few.

There are several obvious variations to the broad invention and thuscome within the scope of the present invention. Uniquely, this inventionmay work with any type of IC; like Js, DIPs, or ZIPs, etc. However, thetest cite station 18 parts will obviously have to be changed toaccommodate for the various IC shapes. These changes would be easy forone skilled in the art.

Additionally, another variation of the invention would involve the wayof ICs are loaded into the testing cite 18. One form would involve usingrobotic pick and place technology. Another form could use a conveyorbelt to collect the ICs from the singulation stations and to load intothe testing device. Of course with these alternative technologies, thetesting device would not have to be angled to use the gravity typefeeding used in the illustrated embodiment of the invention.

While the invention has been taught with specific reference to theseembodiments, someone skilled in the art will recognize that changes canbe made in form and detail without departing from the spirit and thescope of the invention. The described embodiments are to be consideredin all respects only as illustrative and not restrictive. The scope ofthe invention is, therefore, indicated by the appended claims ratherthan by the foregoing description. All changes which come within themeaning and range of equivalency of the claims are to be embraced withintheir scope.

1. An integrated circuit testing apparatus for testing an integratedcircuit leaving an IC singulation station, comprising: a) a receivingmeans positioned in a pre test position for receiving the integratedcircuit from the IC singulation station; b) a testing site, positionedto secure the integrated circuit after a displacement of said receivingmeans to a test position, the displacement positioning said integratedcircuit in said test testing site said testing site having a testconnection for making physical contact with said integrated circuit whenit is secured in said testing site, a circuit test performed on saidintegrated circuit when it is secured in said testing site; and c) aholding station having a first post test position and a second post testposition, said holding station receiving the integrated circuit in saidfirst post test position from the receiving means following a return ofthe receiving means to said pre test position subsequent to theperforming of the circuit test of the integrated circuit; d) a firsttrack for receiving the integrated circuit from the holding station whenthe holding station is in said first post test position and when thecircuit test determines that the integrated circuit has a first testcondition: and e) a second track for receiving the integrated circuitfrom the holding station when the holding station is in said second posttest position, said second test position attained when said receivingmeans returns to said test position, said second track receiving theintegrated circuit when the circuit test determines that the integratedcircuit has a second test condition.
 2. The apparatus of claim 1,wherein the holding station further comprises: a control pin forretaining the integrated circuit in the first post test position, whenthe integrated circuit has said second test condition, and for releasingthe integrated circuit from the first post test position to said firsttrack when said integrated circuit has said first test condition, andfor releasing said integrated circuit from said second post testposition to said second track when said integrated circuit has saidsecond test condition.
 3. A method for testing an integrated circuit ina testing apparatus after a departure of the integrated circuit from anintegrated circuit singulation apparatus comprising the steps of: a)moving the testing apparatus to a loading position; b) loading theintegrated circuit into the testing apparatus; c) moving the testingapparatus to a test position to position the integrated circuit fortesting; d) performing electrical tests on the integrated circuit toprovide a tested integrated circuit having identified first and secondtest conditions; e) moving the testing apparatus from the test positionto position the tested integrated circuit for unloading; f) moving thetested integrated circuit to a first unloading position; g) unloadingthe tested integrated circuit from the first unloading position to afirst track when it has said first test condition; h) moving the testedintegrated circuit to a second unloading position when it has saidsecond test condition; and i) unloading the tested integrated circuitfrom the second unloading position to a second track when it has saidsecond test condition.
 4. The method as specified in claim 3, furthercomprising moving said testing apparatus to said test position duringsaid step of moving the tested integrated circuit to said secondunloading position.
 5. A testing apparatus for controlling positioningof a circuit before, during and after a circuit test is performed on thecircuit, the circuit test determining a first and a second testcondition of the circuit, the apparatus comprising: a) a positioningapparatus having a first port and a second port and capable ofdisplacement to a first position and a second position, said first portreceiving the circuit for testing; b) a testing apparatus for securingsaid circuit during a testing of the circuit, said positioning apparatusdisplaced to said second position during the testing; c) a testingcontrol pin for retaining said circuit in said first port prior to thetesting and for allowing a transfer of said circuit from said first portto said second port subsequent to the testing; d) a first track forreceiving said circuit from said second port when said circuit testfinds said circuit to have the first test condition, said positioningapparatus being in said first position; and e) a second track forreceiving said circuit from said second port when said circuit testfinds said circuit to have the second test condition, said positioningapparatus being in said second position.
 6. The apparatus as specifiedin claim 5, further comprising an unloading control pin for retainingsaid circuit in said second port when said circuit test finds saidcircuit to have said second test condition and said testing apparatus isin said first position and for allowing a release of said circuit tosaid first track when said circuit test finds said circuit to have saidfirst test condition and for allowing a release of said circuit to saidsecond track when said circuit test finds said circuit to have saidsecond test condition.
 7. An integrated circuit testing apparatus fortesting an integrated circuit leaving an integrated circuit singulationstation, comprising: a receiving apparatus positioned to receiveuntested integrated circuits from the integrated circuit singulationstation; a testing apparatus positioned to receive the untestedintegrated circuits from the receiving apparatus and test the integratedcircuits to identify defective integrated circuits and non-defectiveintegrated circuits, the testing apparatus including a holding stationmoveable with the testing apparatus, a first position, and a secondposition, the testing apparatus while in the first position allowingtested integrated circuits to proceed to the holding station andallowing untested integrated circuits to be received from the receivingapparatus; and a separating apparatus connected to the testing apparatusto separate defective integrated circuits from non-defective integratedcircuits after testing thereof, the separating apparatus including afirst track for receiving integrated circuits from the holding stationin the first position, and a second track for receiving integratedcircuits from the holding station in the second position.
 8. Theapparatus of claim 7, wherein the testing apparatus while in the secondposition will electrically test the integrated circuit.
 9. The apparatusof claim 8, further comprising: the holding station while in the firstposition holding defective integrated circuits from proceeding to theseparating apparatus, and allowing non-defective integrated circuits toproceed to the first track of the separating apparatus; and the holdingstation while in the second position releasing defective integratedcircuits to the second track of the separating apparatus.
 10. Anintegrated circuit testing apparatus for testing an integrated circuitleaving an integrated circuit singulation station, comprising: a loadingapparatus for supplying the integrated circuit leaving the integratedcircuit singulation station to the integrated circuit testing apparatus;a receiving apparatus positioned to receive untested integrated circuitsfrom the integrated circuit singulation station; a testing apparatuspositioned to receive the untested integrated circuits from thereceiving apparatus and test the integrated circuits to identifydefective integrated circuits and non-defective integrated circuits, thetesting apparatus including a holding station, a first position, and asecond position, the testing apparatus while in the first positionallowing tested integrated circuits to proceed to the holding stationand allowing untested integrated circuits to be received from thereceiving apparatus; and a separating apparatus connected to the testingapparatus to separate defective integrated circuits from non-defectiveintegrated circuits after testing thereof, the separating apparatusincluding a first track for receiving non-defective integrated circuitsfrom the holding station in the first position and a second track forreceiving defective integrated circuits from the holding station in thesecond position.
 11. The apparatus of claim 10, wherein the testingapparatus while in the second position will electrically test theintegrated circuit.
 12. The apparatus of claim 11, further comprising:the holding station while in the first position holding defectiveintegrated circuits from proceeding to the separating apparatus, andallowing non-defective integrated circuits to proceed to the first trackof the separating apparatus; and the holding station while in the secondposition releasing defective integrated circuits to the second track ofthe separating apparatus.
 13. A method of testing an integrated circuitin a testing apparatus having a test site, a holding station, anon-defective integrated circuit track, a defective integrated circuittrack, a first position, and a second position, after singulation of theintegrated circuit in an integrated circuit singulation apparatus, themethod comprising: transferring the integrated circuit from theintegrated circuit singulation apparatus; receiving the integratedcircuit at the testing apparatus while the testing apparatus is in thefirst position; moving the testing apparatus to the second position;testing the integrated circuit to identify defective and non-defectiveconditions of the integrated circuit; moving the testing apparatus tothe first position to allow the tested integrated circuit to proceed tothe holding station in a first unloading position while receiving asecond singulated integrated circuit into the testing apparatus;allowing non-defective integrated circuits to proceed to thenon-defective integrated circuit track from the first unloadingposition; and moving the holding station to a second unloading positionand allowing defective integrated circuits to proceed to the defectiveintegrated circuit track.
 14. A method of testing an integrated circuitafter singulation thereof using a testing apparatus having a test site,a holding station, a non-defective integrated circuit track, a defectiveintegrated circuit track, a first position, and a second position, themethod comprising: transferring the integrated circuit from theintegrated circuit singulation apparatus; receiving the integratedcircuit at the testing apparatus while the testing apparatus is in thefirst position; moving the testing apparatus to the second position;testing the integrated circuit thereby identifying defective andnon-defective conditions thereof; moving the testing apparatus to thefirst position after testing of the integrated circuit; allowing thetested integrated circuit to proceed to the holding station in a firstunloading position; receiving a second singulated integrated circuitinto the testing apparatus while in the first position; unloadingnon-defective integrated circuits to the non-defective integratedcircuit track from the first unloading position; and moving the holdingstation to a second unloading position and unloading defectiveintegrated circuits to the defective integrated circuit track.
 15. Amethod of testing an integrated circuit in a testing apparatus having atest site, a holding station, a non-defective integrated circuit track,a defective integrated circuit track, a first position, and a secondposition, after singulation of the integrated circuit in an integratedcircuit singulation apparatus, the method comprising: receiving theintegrated circuit at the testing apparatus while the testing apparatusis in the first position; moving the testing apparatus to the secondposition; testing the integrated circuit to identify defective andnon-defective conditions of the integrated circuit; moving the testingapparatus to the first position to allow the tested integrated circuitto proceed to the holding station in a first unloading position whilereceiving a second singulated integrated circuit into the testingapparatus; allowing non-defective integrated circuits to proceed to thenon-defective integrated circuit track from the first unloadingposition; and moving the holding station to a second unloading positionand allowing defective integrated circuits to proceed to the defectiveintegrated circuit track.
 16. A method of testing an integrated circuitafter the singulation thereof using a testing apparatus having a testsite, a holding station, a non-defective integrated circuit track, adefective integrated circuit track, a first position, and a secondposition, the method comprising: receiving the integrated circuit at thetesting apparatus while the testing apparatus is in the first position;moving the testing apparatus to the second position; testing theintegrated circuit thereby identifying defective and non-defectiveconditions thereof; moving the testing apparatus to the first positionafter testing of the integrated circuit; allowing the tested integratedcircuit to proceed to the holding station in a first unloading position;receiving a second singulated integrated circuit into the testingapparatus while in the first position; unloading non-defectiveintegrated circuits to the non-defective integrated circuit track fromthe first unloading position; and moving the holding station to a secondunloading position and unloading defective integrated circuits to thedefective integrated circuit track.
 17. An apparatus for testingsingulated integrated circuits, comprising: a testing apparatus movablebetween a first position and a second position receiving untestedintegrated circuits while in the first position and identifying firstand second test conditions of an integrated circuit while in the secondposition; a holding station coupled to the testing apparatus and movablebetween the first position and the second position, the holding stationreceiving tested integrated circuits from the testing apparatus while inthe first position and releasing tested integrated circuits having thefirst test condition while at the first position and releasing testedintegrated circuits having the second test condition while at the secondposition; a first track for receiving tested integrated circuits havingthe first test condition from the holding station when the holdingstation is at the first position; and a second track for receivingtested integrated circuits having the second test condition from theholding station when the holding station is at the second position. 18.The apparatus of claim 17, wherein the testing apparatus and the holdingstation include at least one integral member moveable between the firstposition and the second position.
 19. A method of testing singulatedintegrated circuits in a testing apparatus having a first position, asecond position, a first integrated circuit track, a second integratedcircuit track, and a holding station, comprising: receiving an untested,singulated integrated circuit into the testing apparatus while in thefirst position; moving the untested, singulated integrated circuit tothe second position; testing the untested, singulated integrated circuitto determine first and second test conditions thereof; moving thetested, singulated integrated circuit back to the first position;allowing the tested, singulated integrated circuit to move to theholding station in the first position; receiving another untested,singulated integrated circuit into the testing apparatus while in thefirst position; releasing tested, singulated integrated circuits havingthe first test condition to the first integrated circuit track while theholding station is in the first position; and releasing tested,singulated integrated circuits having the second test condition to thesecond integrated circuit track while the holding station is in thesecond position.
 20. An apparatus for testing singulated integratedcircuits, comprising: a loading apparatus for supplying an integratedcircuit leaving an integrated circuit singulation station to theapparatus; a testing apparatus movable between a first position and asecond position for receiving untreated integrated circuits while in thefirst position and identifying first and second test conditions of anintegrated circuit while in the second position; a holding stationcoupled to the testing apparatus and movable between the first positionand the second position, the holding station receiving tested integratedcircuits from the testing apparatus while in the first position andreleasing tested integrated circuits having the first test conditionwhile at the first position and releasing tested integrated circuitshaving the second test condition while at the second position; a firsttrack for receiving tested integrated circuits having the first testcondition from the holding station when the holding station is at thefirst position; and a second track for receiving tested integratedcircuits having the second test condition from the holding station whenthe holding station is at the second position.
 21. The apparatus ofclaim 20, wherein the testing apparatus and the holding station includeat least one integral member moveable between the first position and thesecond position.
 22. A method of testing singulated integrated circuitsin a testing apparatus having a first position, a second position, afirst integrated circuit track, a second integrated circuit track, and aholding station, comprising: transferring the integrated circuit fromthe integrated circuit singulation apparatus; receiving an untested,singulated integrated circuit into the testing apparatus while in thefirst position; moving the untested, singulated integrated circuit tothe second position; testing the untested, singulated integrated circuitto determine first and second test conditions thereof; moving thetested, singulated integrated circuit back to the first position;allowing the tested, singulated integrated circuit to move to theholding station in the first position; receiving another untested,singulated integrated circuit into the testing apparatus while in thefirst position; releasing tested, singulated integrated circuits havingthe first test condition to the first integrated circuit track while theholding station is in the first position; and releasing tested,singulated integrated circuits having the second test condition to thesecond integrated circuit track while the holding station is in thesecond position.